A PHY Configuration consists of:

Each Lane Module communicates with its counterpart across the interconnect using two signal lines.

Functional Components of a Lane Module

Each Lane Module contains:

Signal characteristics:

Usage:

The Lane Control and Interface Logic coordinates all functions and interfaces with higher-level protocol layers.

Universal Lane Module Functions.png


What Happens Inside a Lane Module?

Mode Purpose Speed Signal Strength How it Works
High-Speed (HS) Sending big data fast (like video frames) Very fast Small voltage (tiny electrical changes) Uses both wires together as a pair (differential)
Low-Power (LP) Sending small control commands (like start/stop) Slow Larger voltage Uses each wire individually (single-ended)
There is also an optional Alternate Low-Power (ALP) mode for special low-power communication.

High-Speed Functions

A Lane may contain:

When enabled, HS blocks provide termination for the lane.
When disabled, they enter high-impedance state.


Low-Power Functions

LP functions consist of:

LP-CD checks for line contention (avoid both sides driving at once) before driving new states (except in ULPS).


Alternate Low-Power (ALP) Functions (Optional)

Available when ALP mode is supported:

ALP mode shares HS-TX / HS-RX hardware, with ALP-ED added for detecting exit conditions.


Functional Correlation Rules

If the Lane has… It must also include…
HS-TX LP-TX
HS-RX LP-RX and (if ALP supported) ALP-ED
Additionally:

The HS-TX, LP-TX, and HS-RX functions never operate simultaneously except during short transition periods.


Lane Matching Requirement

For correct operation: